The Anti-Tamper Digital Clocks Diaries
The Anti-Tamper Digital Clocks Diaries
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implies for analyzing that works by using the plurality of delayed monotone indicators to detect a clock fault and
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Another element of the invention may reside within an apparatus for detecting voltage tampering, comprising a circuit that provides a monotone signal, a plurality of resettable hold off line segments, and an Assess circuit: The circuit gives a monotone signal through an Examine time frame. The plurality of resettable delay line segments hold off the monotone signal to create a respective plurality of delayed monotone indicators.
What is claimed is: one. A method for detecting clock tampering, comprising: delivering a plurality of resettable delay line segments, whereby resettable delay line segments among a resettable hold off line phase associated with a minimal delay time in addition to a resettable hold off line section affiliated with a highest hold off time are Every single associated with discretely escalating hold off moments;
37. An equipment for detecting voltage tampering, comprising: a circuit that gives a monotone sign throughout an Examine time frame;
Disclosed is a technique for detecting clock tampering. In the method a plurality of resettable hold off line segments are provided. Resettable delay line segments between a resettable delay line segment associated with a minimum delay time in addition to a resettable delay line segment related to a utmost hold off time are Every single affiliated with discretely escalating delay periods.
38. The apparatus for detecting voltage tampering as defined in assert 37, whereby the resettable delay line segments are reset for the duration of a reset period of time, whereby the reset time frame is prior to the evaluate time frame.
The delay among the reset operators of one other sensing circuits can be significantly less stringent and should be determined by the highest acceptable operating frequency.
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Yet another aspect of the invention may perhaps reside in an equipment for detecting clock tampering, comprising: implies for furnishing a monotone sign throughout a clock Consider time frame connected with a clock; means for delaying the monotone signal utilizing a plurality of resettable delay line segments to create a respective plurality of delayed monotone signals acquiring discretely rising hold off moments concerning a minimum amount delay time and a most hold off time; and suggests for using the clock to bring about an evaluate circuit that uses the plurality Anti-Tamper Digital Clocks of delayed monotone signals to detect a clock fault.